1. Field of the Invention
The present invention relates to a pixel data compression and decompression method and device thereof. More particularly, the present invention relates to a pixel data compression and decompression method and device thereof applicable to digital television.
2. Description of the Related Art
In multi-media transmission technology, digital television has become increasingly important. For example, in order to provide a list of multi-media services such as interactive television, television shopping and video-on-demand (VOD) service to every family within the USA, the Federal Communications Commission (FCC) has requested that all televisions produced after 2006 should include a built-in digital tuner. In addition, as a response to the new generation of digital broadcasting in the USA, Europe and Japan, the use of high definition (HD) digital broadcasting system for transmitting clearer images has become the upcoming trend. Accompanying the rapid development in HD broadcasting and digital television, the suppliers in various fields such as chip manufacturers and system providers gather to form unions with the common goal of developing the digital television and related markets.
One of the critical components of a digital television system is the pixel data processing device. The digital television system obtains video signals from an input channel. The pixel data processing device can rely on various image-processing techniques to enhance the quality of the video signals and output the processed video signals to the cathode ray tube or television panel suitable for display. Therefore, the pixel data processing device can directly affect the user's perception of video quality. At present, the picture resolution of a high definition television (HDTV) has raised to 1920×1080 pixels. Thus, the mass of data that needs to be processed at any one time by the HDTV is roughly six times of a conventional television. In other words, the newer generation of pixel data processing devices not only has to provide clear images, but also requires a strong computational capacity For processing substantial amount of high picture quality data. To satisfy the present and future processing requirements of high definition television, the inventors have to provide an innovative design that can reduce overall data bandwidth.
FIG. 1 is a block diagram of a conventional pixel data processing device 100. As shown in FIG. 1, the video input coming from an input channel will be individually pre-processed inside a pre-processing unit 101. The pre-processor includes an analogue-to-digital (AD) converter or a video decoder, for example. When the line buffer 102 of the pre-processor is fully loaded, the memory management unit 104 will write the pre-processed data from the line buffer 102 into the memory 104. On the other hand, the image-processing unit 106 will read video data through the memory management unit 103 and transfer to the line buffer 105. The image-processing unit 106 can perform complicated image-processing algorithms such as de-interlacing, color processing, noise canceling or contrast enhancing. Therefore, the image-processing unit 106 is often designed with a high operating efficiency and parallel processing architecture.
However, the image-processing unit 106 of the pixel data processing device 100 has to wait until the pixel data to be processed is ready in the line buffer 105. Therefore, the problem of having insufficient frequency bandwidth in the memory management unit 103 is frequently encountered. A direct solution to this problem includes increasing the clock rate and width of the memory data bus. Yet, this will increase the production cost significantly. Other examples, including the U.S. Pat. Nos. 5,869,198 and 6,570,626, can reduce the graphic data bandwidth but provide no direct solution to the video data bandwidth problem.